Title:  Senior Specialist, Field-Programmable Gate Array Design Engineer

Job Title: Senior Specialist, Field-Programmable Gate Array Design Engineer
Job Code: 33803
Job Location: Salt Lake City, Utah
Job Schedule: 9/80 (Every other Friday off!)

Job Description:
L3Harris is looking for a talented FPGA design engineer with industry experience in wireless digital communications, modems, networking, and/or digital signal processing (DSP).  We design advanced wireless digital communication systems and electronic warfare systems.  Development efforts include the whole lifecycle of designs from proposals, requirement definition, coding, simulation, synthesis, place and route, verification testing, and system support.  We are looking for an engineer who enjoys challenging work with a team of talented engineers and can work well both with a team and as an individual contributor. Salt Lake City provides incredible year-round outdoor recreation options and cultural experiences, and L3Harris values your work/life balance so you can enjoy these opportunities.

Essential Functions:
•    Modulation
•    Demodulation
•    Digital filters
•    Forward Error Correction (FEC)
•    Electronic Warfare
•    Networking
•    Industry standard interfaces (e.g. 10/100/1000 Ethernet, SPI, UART, SDRAM, DDR3, JESD, PCIe, Ethernet).
•    FPGA verification through simulation and unit testing.
•    Must be able to obtain a US security clearance.

Qualifications:
•    Bachelor’s Degree and minimum 6 years of prior relevant experience. Graduate Degree and a minimum of 4 years of prior related experience. In lieu of a degree, minimum of 10 years of prior related experience. 
•    Ability to obtain Secret security clearance

Preferred Additional Skills:
•    6+ years FPGA design experience
•    Experience in either VHDL (preferred) or Verilog development languages.
•    Experience implementing complex modem and/or DSP circuits in programmable logic using FPGA devices.  Equivalent experience in ASIC design is also applicable.
•    Experience in simulation, synthesis, and placement software tools such as ModelSim, Synplicity, Xilinx Vivado / ISE and/or Altera Quartus development tool sets.
•    Experience with HLS (High-Level Synthesis)
•    Experience with timing closure in large FPGAs.
•    Experience in laboratory debug techniques using digital scopes, logic analyzers, BERTS, and other complex measurement devices.
•    FPGA Design using High-speed serial interfaces (3+ Gbps)
•    Familiarity with code revision management tools such as Git/Clearcase.
•    Familiarity with C/C++/C# and Matlab/Simulink.
•    Active Secret Clearance