Title:  Lead, Electrical Engineering - FPGA Verif. Palm Bay

Job Title: Lead, FPGA Verification, UVM
Job Code: 28719
Job Location: Palm Bay, FL
Job Schedule: 9/80 (Every other Friday off!)
Relocation: Relocation assistance is available to qualified applicants

Job Description: Seeking talented UVM/Design Verification Engineer, able to work in teams and independently, learn quickly and be productive in a fast paced, dynamic environment.

Essential Functions: 
•    Execute and contribute to the FPGA verification plan
•    Architect UVM chip level verification environments for multiple FPGAs
•    Develop reusable agents, top level testbench modules and environments
•    Define and implement functional coverage model based upon DUT requirements and close code coverage.
•    Utilize UVM to create drivers, monitors, predictors, and scoreboards based on DUT requirements.
•    Strong understanding of FPGA design process including requirements generation, preliminary design, peer reviews, detailed design, test plan generation, and integration and test.
•    Work independently to develop test bench solutions.

Qualifications:
•    BS Degree in electrical/computer engineering and 9+ years of professional experience, OR, a Masters in electrical/computer engineering and 7+ years of professional experience OR minimum 13 years of prior experience in lieu of degree
•    5 Years of experience with and understanding of Altera or Xilinx / AMD FPGA architectures
•    5 years of experience with VHDL
•    Ability to obtain a US Security Clearance

Preferred Additional Skills:
•    Experience in ASIC / FPGA verification using C/C++ and/or System Verilog
•    Experience with DO-254 air worthiness certification
•    Experience with building and setting up scalable simulation/verification environments.
•    Experience with and understanding of Altera and/or Xilinx FPGA architectures.
•    Experience with Vivado and/or Quartus tool suite.
•    Proficiency with hardware verification languages: System Verilog, System Verilog Assertions
•    Experience with high speed serial protocols (PCI Express, SRIO, Ethernet)
•    Experience designing 10G Ethernet based Network Interface Designs
•    Experience in network protocols including IPv6 and UDP
•    Experience with SoC (Kintex UltraScale/UltraScale+, Virtex UltraScale/UltraScale+, Zynq UltraScale)
•    Proficiency with Object Oriented Programming Concepts: Inheritance, Polymorphism, etc.
•    Proficient in scripting languages: bash/csh, Perl, Python, etc.
•    Revision Control Systems: svn, git
•    Proficient in Linux Environments
•    Constrained Random Verification Experience highly desired.
•    Experience with packet-based protocols (PCI Express etc.), Network-centric designs (Ethernet, IP, FC).
•    Experience with high speed memory interfaces (DDRx)
•    Familiarity with test scoping for complex designs, code coverage, functional coverage, assertions.
•    Ability to focus on finding design issues, corner cases and out of box ideas to make designs more robust