Title:  Electrical Engineer Intern - FPGA Design (Camden, NJ)

Job Title:  ASIC/FPGA VHDL Design Engineer (Entry Level)

Job Code: EEIC

Job Location: Camden, NJ

Schedule: 9/80

Job Description:

Reporting to the Manager, Engineering (ASIC/FPGA), the intern Member of Engineering Staff (AMES) will be part of the key design team, responsible for the delivery of FPGAs for defense applications. S/he will architect, implement FPGA design, with hands on design/debug with primarily Ethernet,  I2C, SPI, AXI protocols.

L3Harris has state-of-the-art EDA flows/methodologies including Mentor EDA: Simulator Questa Prime, Verification IP (QVIPs), UVM framework, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), Questa Lint, Synopsys (DC/Primetime/Synplify), Xilinx/Intel/Microchip EDA (Vivado/Libero/Quartus).  We are a learning organization and have the capability to target all FPGA vendors and have ASIC front end capability, with mature design processes. 

This is a high impact role in the organization to ensure robust quality and delivery of communication products for National Security. 

Essential Functions:

• Derive FPGA design specifications from system requirements
• Develop detailed FPGA architecture for implementation
• Implement design in RTL (VHDL) and perform module level simulations
• Perform Synthesis, Place and Route (PAR) and Static Timing Analysis (STA)
• Perform RTL quality using: Lint, Reset Domain Crossing (RDC), Clock Domain Crossing (CDC) , Static Formal EDA
• Generate verification test plans and perform End to End Simulations
• Support Board, FPGA bring up
• Validate design through HW/SW integration test with test equipment
• Support product collateral for NSA certification

Qualifications: 

• Bachelor of Science (BS) -Four year degree or Masters (MS) or PhD from an accredited course of study in engineering, engineering technology (chemistry, physics, mathematics, data science, or Electrical/Electronics/Computer Engineering/Computer Science)

Preferred Additional Skills:

• Experience with mapping algorithms to architecture
• Experience in C++ (OOP)
• Experience with any of protocols : Ethernet, TCP/IP, PCIe, NVMe, USB
• Experience with Xilinx SoC design with SDKs and PetaLinux OS
• Experience with High-Level Synthesis (HLS) with Vivado HLX or Mentor Catapult
• Experience with Xilinx FPGAs and Vivado
• Experience with Revision control system
• Experience with Earned Value Management (EVM)
• Good written, verbal, and presentation skills
• Experience designing FPGA products with VHDL
• Active DoD Security Clearance

In compliance with pay transparency requirements, the salary range for this role in California, Massachusetts, New Jersey, Washington, and the Greater D.C, Denver, or NYC areas is $25.00 - $47.50. The salary range for this role in Colorado state, Hawaii, Illinois, Maryland, Minnesota, New York state, and Vermont is $22.00 - $40.50. This is not a guarantee of compensation or salary, as final offer amount may vary based on factors including but not limited to experience and geographic location. L3Harris also offers a variety of benefits, including relocation stipend, 401(k), EAP, and company-paid holidays. The specific programs and options available to an employee may vary depending on date of hire, schedule type, and the applicability of collective bargaining agreements.